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Sun, Nov 1, 2026 10
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Fix: MLX arrays created on the consuming thread only (worker/stacked-layout stream error)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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H4: fused up+gate option (bit-identical, no end-to-end gain), D-011, LOG
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Cold sweep complete, host-time attribution, Gate D profiling (latency-bound), remote cost breakdown; thresholded predictors; LOG/DECISIONS D-010
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Gate E: authenticated TCP transport, expert worker, remote executor with local fallback (localhost bit-identical), distributed bench, power sampler, LOG
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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SSD tier: parallel demand reads + expert-contiguous TITAN layout (cold 16-slot 8-10 -> 36 tok/s); sim v2 results; probe fix; LOG/DECISIONS
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Qwen3-30B parity on M3U96a (bit-identical, 121.7 vs 121.5 tok/s), make_tables.py, cold-NVMe sweep script, LOG
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Paper skeleton v0.1 (protocol + preliminary), README, models config, stacked-layout registry (Qwen3-30B), generalized tests
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Gate C: predictors (prev_rank, transition depth d, probe), trace simulator, async prefetcher, lazy installs, miss-cost breakdown, v2 traces, LOG/DECISIONS
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Gate B/C: sync-free fast path, bench_decode, capacity sweep, routing traces, link/net probes, LOG
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Gate A/B: scaffold, mandate, inventory tooling, prior art (59 refs), registry/store/slot-table runtime, numerical tests bit-identical to mlx-lm
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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